The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting thread-level parallelism (TLP) and data-level parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future.
The NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) (NSF 19-598) will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore’s Law.
If you are interesting in applying for this funding opportunity, please start a routing sheet as soon as possible. As a reminder, proposals must be completed and submitted to OSRP at least two business days prior to the deadline of November 20, 2019. If you should have any questions, please contact OSRP.